View SCN68562_4708140.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SCN68562 dual universal serial communications controller (duscc) product specification ic19 data handbook 1995 may 01 integrated circuits
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 2 1995 may 01 853-0831 15179 description the philips semiconductors SCN68562 dual universal serial communications controller (duscc) is a single-chip mos-lsi communications device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. it supports bit-oriented and character-oriented (byte count and byte control) synchronous data link controls as well as asynchronous protocols. the SCN68562 interfaces to the 68000 mpus via asynchronous bus control signals and is capable of program-polled, interrupt driven, block-move or dma data transfers. the operating mode and data format of each channel can be programmed independently. each channel consists of a receiver, a transmitter, a 16-bit multifunction counter/timer, a digital phase-locked loop (dpll), a parity/crc generator and checker, and associated control circuits. the two channels share a common bit rate generator (brg), operating directly from a crystal or an external clock, which provides 16 common bit rates simultaneously. the operating rate for the receiver and transmitter of each channel can be independently selected from the brg, the dpll, the counter/timer, or from an external 1x or 16x clock, making the duscc well suited for dual-speed channel applications. data rates up to 4mbits per second are supported. the transmitter and receiver each contain a four-deep fifo with appended transmitter command and receiver status bits and a shift register. this permits reading and writing of up to four characters at a time, minimizing the potential of receiver overrun or transmitter underrun, and reducing interrupt or dma overhead. in addition, a flow control capability is provided to disable a remote transmitter when the fifo of the local receiving device is full. two modem control inputs (dcd and cts) and three modem control outputs are provided. these inputs and outputs can be optionally programmed for other functions. features general features ? dual full-duplex synchronous/asynchronous receiver and transmitter ? multiprotocol operation bop: hdlc/adccp, sdlc, sdlc loop, x.25 or x.75 link level, etc. cop: bisync, ddcmp async: 58 bits plus optional parity ? four character receiver and transmitter fifos pin configurations 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 21 22 23 24 iackn a3 a2 a1 rtxdakbn/ irqn resetn rtsbn/ trxcb rtxcb dcdbn/ txdakbn/ rtxdrqbn/ txdrqbn/ ctsbn/lcbn d7 d6 d5 d4 dtackn dtcn gnd csn donen d3 d2 d1 d0 ctsan/lcan txdrqan/ rtxdrqan/ txdakan/ txda dcdan/ rtxca trxca rtsan/ x2/idcn x1/clk rtxdakan/ a6 a5 a4 v dd n package gpi1bn synoutbn synibn rxdb txdb gpi2bn gpo1bn gpo2bn/rtsbn r/wn gpo2an/rtsan gpo1an gpi2an rxda synian synoutan gpi1an dip pin function pin function 1 iackn 27 csn 2 a3 28 r/wn 3 a2 29 donen 4a1 30d3 5 rtxdakbn/ 31 d2 gpi1bn 32 d1 6 irqn 33 d0 7nc 34nc 8 resetn 35 ctsan/lcan 9 rtsbn/ 36 txdrqan/ synoutbn gpo2an/rtsan 10 trxcb 37 rtxdrqan/ 11 rtxcb gpo1an 12 dcdbn/ 38 txdakan/ synibn gpi2an 13 nc 39 txda 14 rxdb 40 rxda 15 txdb 41 nc 16 txdakbn/ 42 dcdan/ gpi2bn synian 17 rtxdrqbn/ 43 rtxca gpo1bn 44 trxca 18 txdrqbn/ 45 rtsan/ gpo2bn/rtsbn synoutan 19 ctsbn/lcbn 46 x2/idcn 20 d7 47 x1/clk 21 d6 48 rtxdakan/ 22 d5 gpi1an 23 d4 49 a6 24 dtackn 50 a5 25 dtcn 51 a4 26 gnd 52 v dd 1 46 20 33 47 34 21 8 plcc 7 top view index corner a package sd00222 figure 1. pin configurations
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 3 ? 0 to 4mhz data rate ? programmable bit rate for each receiver and transmitter selectable from: 16 fixed rates: 50 to 38.4k baud one user-defined rate derived from programmable counter/timer external 1x or 16x clock digital phase-locked loop ? parity and fcs (frame check sequence lrc or crc) generation and checking ? programmable data encoding/decoding: nrz, nrzi, fm0, fm1, manchester ? programmable channel mode: full- and half-duplex, auto-echo, or local loopback ? programmable data transfer mode: polled, interrupt, dma, wait ? dma interface compatible with the philips semiconductors scb68430 direct memory access interface (dmai) and other dma controllers single- or dual-address dual transfers half- or full-duplex operation automatic frame termination on counter/timer terminal count or dma done ? interrupt capabilities daisy chain option vector output (fixed or modified by status) programmable internal priorities maskable interrupt conditions ? multi-function programmable 16-bit counter/timer bit rate generator event counter count received or transmitted characters delay generator automatic bit length measurement ? modem controls rts, cts, dcd, and up to four general i/o pins per channel cts and dcd programmable autoenables for tx and rx programmable interrupt on change of cts or dcd ? on-chip oscillator for crystal ? ttl compatible ? single +5v power supply asynchronous mode features ? character length: 5 to 8 bits ? odd or even parity, no parity, or force parity ? up to two stop bits programmable in 1/16-bit increments ? 1x or 16x rx and tx clock factors ? parity, overrun, and framing error detection ? false start bit detection ? start bit search 1/2-bit time after framing error detection ? break generation with handshake for counting break characters ? detection of start and end of received break ? character compare with optional interrupt on match ? transmits up to 4mbs and receive up to 2mbps data rates character-oriented protocol features ? character length: 5 to 8 bits ? odd or even parity, no parity, or force parity ? lrc or crc generation and checking ? optional opening pad transmission ? one or two syn characters ? external sync capability ? syn detection and optional stripping ? syn or mark line-fill on underrun ? idle in mark or syns ? parity, fcs, overrun, and underrun error detection bisync features ebcdic or ascii header, text and control messages syn, dle stripping eom (end of message) detection and transmission auto transparent mode switching auto hunt after receipt of eom sequence (with closing pad check after eot or nak) control character sequence detection for both transparent and normal text bit-oriented protocol features ? character length: 5 to 8 bits ? detection and transmission of residual character: 07 bits ? automatic switch to programmed character length for 1 field ? zero insertion and deletion ? optional opening pad transmission ? detection and generation of flag, abort, and idle bit patterns ? detection and generation of shared (single) flag between frames ? detection of overlapping (shared zero) flags ? abort, abort-flags, or fcs flags line-fill on underrun ? idle in mark or flags ? secondary address recognition including group and global address ? single- or dual-octet secondary address ? extended address and control fields ? short frame rejection for receiver ? detection and notification of received end of message ? crc generation and checking ? sdlc loop mode capability
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 4 ordering information description v cc = +5v + 5%, t a = 0 c to +70 c dwg # description serial data rate = 4mbps maximum dwg # 48-pin plastic dual in-line package (dip) SCN68562c4n48 sot240-1 52-pin plastic leaded chip carrier (plcc) package SCN68562c4a52 sot238-3 note: see scn26562/SCN68562 user's guide for detailed description of all the features. block diagram channel mode and timing a/b ctcra/b ctprha/b ctprla/b internal bus dpll clk mux a/b dpll a/b brg counter/ timer a/b c/t clk mux a/b ctha/b ctla/b transmit a/b trans clk mux tpra/b ttra/b tx shift reg crc gen transmit 4 deep fifo spec char gen logic receiver a/b rpra/b rtra/b s1ra/b rcvr clk mux s2ra/b rcvr shift reg receiver 4 deep fifo crc accum bisync compare logic txd a/b rxd a/b interface/ operation control ictsra/b gsr cmr1a/b address decode dma control cmr2a/b omra/b r/w decode ccra/b pcra/b rsra/b trsra/b icra/b iera/b ivr ivrm interrrupt control oscillator special function pins dma interface mpu interface bus buffer d0-d7 dtackn rwn a1-a6 csn resetn rtxdrqan/gpo1an rtxdrqbn/gpo1bn txdrqan/gpo2an txdrqbn/gpo2bn rtxdakan/gpi1an rtxdakbn/gpi1bn txdakan/gpi2an txdakbn/gpi2bn dtcn donen trxca/b rtxca/b rtsbn/synoutbn rtsan/synoutan ctsa/bn dcdbn/synibn dcdan/synian irqn iackn x1/clk x2/idcn duscc logic control sd00223 figure 2. block diagram
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 5 pin description in this data sheet, signals are discussed using the terms `active' and `inactive' or `asserted' and `negated' independent of wh ether the signal is active in the high (logic 1) or low (logic 0) state. n at the end of a pin name signifies the signal associated with the pin i s active-low (see individual pin description for the definition of the active level of each signal.) pins which are provided for both channels ar e designated by a/b after the name of the pin and the active-low state indicator, n, if applicable. a similar method is used for registers provide d for both channels: these are designated by either an underline or by a/b after the name. mnemonic dip pin no. type name and function a1 a6 4-2, 45-47 i address lines: active-high. address inputs which specify which of the internal registers is accessed for read/write operation. d0 d7 31-28, 21-18 i/o bidirectional data bus: active high, 3-state. bit 0 is the lsb and bit 7 is the msb. all data, command, and status transfers between the cpu and the duscc take place over this bus. the data bus is enabled when csn is low, during interrupt acknowledge cycles and single-address dma acknowledge cycles. r/wn 26 i read/write: a high input indicates a read cycle and a low input indicates a write cycle when a cycle is initiated by assertion of the csn input. csn 25 i chip select: active-low input. when low, data transfers between the cpu and the duscc are enabled on d0 d7 as controlled by the r/wn and a1 a6 inputs. when csn is high, the duscc is isolated from the data bus (except during interrupt acknowledge cycles and single-address dma transfers) and d0 d7 are placed in the 3-state condition. dtackn 22 o data transfer acknowledge: active-low, 3-state. dtackn is asserted on a write cycle to indicate that the data on the bus has been latched, and on a read cycle or interrupt acknowledge cycle to indicate valid data is on the bus. the signal is negated when completion of the cycle is indicated by negation of the csn or iackn input, and returns to the inactive state (3-state) a short period after it is negated. in a single address dma mode, data is latched with the falling edge of dtcn. dtackn is negated when completion of the cycle is indicated by the assertion of dtcn or negation of dma acknowledge inputs (whichever occurs first), and returns to the inactive state (3-state) a short period after it is negated. when negated, dtackn becomes an open-drain output and requires an external pull-up resistor. irqn 6 o interrupt request: active-low, open-drain. this output is asserted upon occurrence of any enabled interrupting condition. the cpu can read the general status register to determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle to cause the duscc to output an interrupt vector on the data bus. iackn 1 i interrupt acknowledge: active-low. when iackn is asserted, the duscc responds by placing the contents of the interrupt vector register (modified or unmodified by status) on the data bus and asserting dtackn. if no active interrupt is pending, dtackn is not asserted. x1/clk 43 i crystal or external clock: when using the crystal oscillator, the crystal is connected between pins x1 and x2. if a crystal is not used, and external clock is supplied at this input. this clock is used to drive the internal bit rate generator, as an optional input to the counter/timer or dpll, and to provide other required clocking signals. x2/idcn 42 o crystal or interrupt daisy chain: when a crystal is used as the timing source, the crystal is connected between pins x1 and x2. this pin can be programmed to provide and interrupt daisy chain active-low output which propagates the iackn signal to lower priority devices, if no active interrupt is pending. this pin should be grounded when an external clock is used on x1 and x2, is not used as an interrupt daisy chain output. resetn 7 i master reset: active-low. a low on this pin resets the transmitters and receivers and resets the registers shown in table 1 of the cduscc users' guide. reset in asynchronous, i.e., no clock is required. rxda, rxdb 37, 12 i channel a (b) receiver serial data input: the least significant bit is received first. if external receiver clock is specified for the channel, the input is sampled on the rising edge of the clock. txda, txdb 36, 13 o channel a (b) transmitter serial data output: the least significant bit is transmitted first. this output is held in the marking (high) condition when the transmitter is disabled or when the channel is operating in local loopback mode. if external transmitter clock is specified for the channel, the data is shifted on the falling edge of the clock. rtxca, rtxcb 39, 10 i/o channel a (b) receiver/transmitter clock: as an input, it can be programmed to supply the receiver, transmitter, counter/timer, or dpll clock. as an output, can supply the counter/timer output, the transmitter shift clock (1x), or the receiver sampling clock (1x). the maximum external receiver/transmitter clock frequency is 4mhz.
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 6 pin description (continued) mnemonic dip pin no. type name and function trxca, trxcb 40, 9 i/o channel a (b) transmitter/receiver clock: as an input, it can supply the receiver, transmitter, counter/timer, or dpll clock. as an output, it can supply the counter/timer output, the dpll output, the transmitter shift clock (1x), the receiver sampling clock (1x), the transmitter brg clock (16x), the receiver brg clock (16x), or the internal system clock (x1/2). the maximum external receiver/transmitter clock frequency is 4mhz. ctsa/bn, lca/bn 32, 17 i/o channel a (b) clear-to-send input or loop control output: active-low. the signal can be programmed to act as an enable for the transmitter when not in loop mode. the duscc detects logic level transitions on this input and can be programmed to generate an interrupt when a transition occurs. when operating in the cop loop mode, this pin becomes a loop control output which is asserted and negated by duscc commands. this output provides the means of controlling external loop interface hardware to go on-line and off-line without disturbing operation of the loop. dcda/bn, synia/bn 38, 11 i channel a (b) data carrier detected or external sync input: the function of this pin is programmable. as a dcd active-low input, it acts as an enable for the receiver or can be used as a general purpose input for the dcd function, the duscc detects logic level transitions on this input and can be programmed to generate an interrupt when a transition occurs. as an active-low external sync input, it is used in cop modes to obtain character synchronization without receipt of a syn character. this mode can be used in disc or tape controller applications or for the optional byte timing lead in x.21. rtxdrqa/bn, gpo1a/bn 34, 15 o channel a (b) receiver/transmitter dma service request or general purpose output: active-low. for half-duplex dma operation, this output indicates to the dma controller that one or more characters are available in the receiver fifo (when the receiver is enabled) or that the transmit fifo is not full (when the transmitter is enabled). for full-duplex dma operation, this output indicates to the dma controller that data is available in the receiver fifo. in non-dma mode, this pin is a general purpose output that can be asserted and negated under program control. txdrqa/bn, gpo2a/bn, rtsa/bn 33, 16 o channel a (b) transmitter dma service request, general purpose output, or request-to-send: active-low. for full-duplex dma operation, this output indicates to the dma controller that the transmit fifo is not full and can accept more data. when not in full-duplex dma mode, this pin can be programmed as a general purpose or a request-to -send output, which can be asserted and negated under program control (see detailed operation). rtxdaka/bn, gpi1a/bn 44, 5 i channel a (b) receiver/transmitter dma acknowledge or general purpose input: active-low. for half-duplex single address dma operation, this input indicates to the duscc that the dma controller has acquired the bus and that the requested bus cycle (read receiver fifo or load transmitter fifo) is beginning. for full-duplex single address dma operation, this input indicates to the duscc that the dma controller has acquired the bus and that the requested read receiver fifo bus cycle is beginning. because the state of this input can be read under program control, it can be used as a general purpose input when not in single address dma mode. txdaka/bn, gp12a/bn 35, 14 i channel a (b) transmitter dma acknowledge or general purpose input: active-low. when the channel is programmed for full-duplex single address dma operation, this input is asserted to indicate to the duscc that the dma controller has acquired the bus and that the requested load transmitter fifo bus cycle is beginning. because the state of this input can be read under program control, it can be used as a general purpose input when not in full-duplex single address dma mode. dtcn 23 i device transfer complete: active-low. dtcn is asserted by the dma controller to indicate that the requested data transfer is complete. donen 27 i/o done: active-low, open-drain. see detailed operation for a description of the function of this pin. rtsa/bn, synouta/bn 41, 8 o channel a (b) sync detect or request-to-send: active-low. if programmed as a sync output, it is asserted one bit time after the specified sync character (cop or bisync modes) or a flag (bop modes) is detected by the receiver. as a request-to-send modem control signal, it functions as described previously for the txdrqn/rtsn pin. v dd 48 i +5v + 10% power input. gnd 24 i signal and power ground input.
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 7 absolute maximum ratings 1 symbol parameter rating unit t a operating ambient temperature 2 0 to +70 c t stg storage temperature -65 to +150 c v cc voltage from v cc to gnd 3 -0.5 to +7.0 v v s voltage from any pin to ground 3 -0.5 to v cc +0.5 v notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this spec ification is not implied. 2. for operating at elevated temperatures, the device must be derated based on +150 c maximum junction temperature and thermal resistance of 40 c/w for plastic dip and 42 c/w for plcc. 3. this product includes circuitry specifically designed for the protection of its internal devices from damaging effects of exc essive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rate d maxima. dc electrical characteristics 1, 4 t a = 0 to +70 c, v cc = 5.0v + 5% symbol parameter test conditions limits unit symbol parameter test conditions min typ max unit v il input low voltage: all except x1/clk 0.8 v x1/clk 0.4 v v ih input high voltage: all except x1/clk 2.0 v x1/clk 2.4 v cc v v ol output low voltage: all except irqn, donen i ol = 5.3ma 0.5 v irqn, donen i ol = 8.8ma 0.5 v v oh output high voltage: (except open drain outputs) i oh = -400 m a 2.4 v i ilx1 x1/clk input low current 3 v in = 0, x2 = gnd -5.5 0.0 ma i ihx1 x1/clk input high current 3 v in = v cc , x2 = gnd 1.0 ma i ilx2 x2 input low current 3 v in = 0, x1 = open -100 m a i ihx2 x2 input high current 3 v in = v cc , x1 = open 100 m a i il input low current dtcn, txdaka/bn, rtxdaka/bn v in = 0 -40 m a i l input leakage current v in = 0 to v cc -5 5 m a i ozh output off current high, 3-state data bus v in = v cc 5 m a i ozl output off current low, 3-state data bus v in = 0 -5 m a i odl open drain output low current in off v in = 0 state: donen -120 -25 m a irqn, dtackn -5 m a i odh open drain output high current in off v in = v cc state: donen, irqn, dtackn 5 m a i cc power supply current v o = 0 to v cc 275 ma c in input capacitance 2 v cc = gnd = 0 10 pf c out output capacitance 2 v cc = gnd = 0 15 pf c i/o input/output capacitance 2 v cc = gnd = 0 20 pf notes: 1. parameters are valid over specified temperature and voltage range. 2. these values were not explicitly tested; they are guaranteed by design and characterization data. 3. x1/clk and x2 are not tested with a crystal installed. 4. this specification applies to revision d, revision e and later revisions.
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 8 ac electrical characteristics 1, 2, 3, 4 t a = -55 to +110 c, v cc = 5v + 10% no figure parameter limits unit no . figure parameter min typ max unit 1 3 resetn pulse width 1.2 m s 2 4,6 a1 - a6 set-up time to csn low 10 ns 3 4,6 a1 - a6 hold time from csn high 0 ns 4 4,6 rwn set-up time to csn low 0 ns 5 4,6 rwn hold time to csn high 0 ns 6 4,6 csn high pulse width 4 160 ns 7 4,5 csn or iackn high from dtackn low 30 ns 7a 5 iackn high to dtackn high 200 ns 8 4,5 data valid from csn or iackn low 300 ns 9 4 data bus floating from csn high 7 100 ns 10 6 data hold time from dtackn low 5 0 ns 11 4,6 dtackn low from read data ready 0 ns 12 4,6 dtackn low from csn low 560 ns 12a 6 csn low to write data valid 50 ns 13 4,6 dtackn high from csn high 150 ns 14 4,6 dtackn high impedance from csn high 185 ns 15 5 dtackn low from iackn low 550 ns 16 8 gpi input set-up time to csn low 20 ns 17 8 gpi input hold time from csn low 100 ns 18 8 gpo output valid from dtackn low 300 ns 19 9 irqn high from: read rxfifo (rxrdy interrupt) 450 ns write txfifo (txrdy interrupt) 8 450 ns write rsr (rx condition interrupt) 8 400 ns write trsr (rx/tx interrupt) 8 400 ns write ictsr (port change and ct int.) 8 400 ns 20 10 x1/clk high or low time 25 ns x1/clk frequency 2.0 14.7456 16 mhz ctclk high or low time 100 ns ctclk frequency 0 4 mhz rxc high or low time 110 ns rxc frequency (16x or 1x) 9 0 4 mhz txc high or low time 110 ns txc frequency (16x or 1x) 0 4 mhz 21 11 txd output from txc input low (1x) (16x) 240 435 ns ns 22 11 txd output from txc output low 50 ns 23 12 rxd data set-up time to rxc high 50 ns 24 12 rxd data hold time from rxc high 50 ns 25 13 iackn low to daisy chain low 200 ns 26 15 data valid from receive dma ackn 300 ns 27 14,15 dtcn width 100 ns 28 14,15 rdyn low to dtcn low 80 ns 29 15 data bus float from dtcn low 7 200 ns 30 14,15 dma ackn low to rdyn (dtackn) low 360 ns 31 14,15 rdyn high from dtcn low 230 ns 32 14,15 rdyn high impedance from dtcn low 250 ns 33 15 receive dma reqn high from dma ackn low 325 ns 34 15 receive dma ackn width 150 ns 35 14,15 receive dma ackn low to donen low 250 ns 36 14 data set-up to dtcn low 50 ns 37 14 data hold from dtcn low 6 50 ns 38 14 transmit dma reqn high from ackn low 340 ns 39 14 transmit dma ackn width 150 ns 40 14 transmit dma ackn low to donen low output 250 ns 40a 14 dtcn low donen output high 260 ns 41 16 csn low to transmit donen low output 300 ns
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 9 no. unit limits parameter figure no. unit max typ min parameter figure 42 16 csn low to transmit dma req negated 400 ns 43 16 csn low to receive donen low 300 ns 44 16 csn low to receive dma req negated 400 ns notes: 1. parameters are valid over specified temperature range. 2. all voltage measurements are referenced to ground (gnd). for dc and functional testing, all inputs except x1/clk swing betwe en 0.8v and 2.0v with a transition time of 20ns maximum. for x1/clk, this swing is between 0.4v and 2.4v all time measurements are refer enced at input voltages of 0.4v and 2.4v for all inputs. output levels are referenced at 1.2v and 2.0v, as appropriate. 3. test conditions for outputs: c l = 150pf, except open-drain outputs. test condition for open-drain outputs: c l = 50pf to gnd, r l = 2.7k w to v cc except dtackn whose r l = 820 w to v cc and c l = 150pf to gnd and donen which requires c l = 50pf to gnd and r l = 1k w to v cc . 4. this specification will impose maximum 68000 cpu clk to 6mhz. higher cpu clk can be used if repeating bus cycles are not per formed. 5. execution of the valid command (after it is latched) requires three falling edges of x1 (see figure 14). 6. in single address dma mode write operation, data is latched by the falling edge of dtcn. 7. these values were not explicitly tested, they are guaranteed by design and characterization data. 8. these timings are from the falling edge of dtackn (not csn rising). 9. x1/clk frequency must be at least four times the receiver serial data rate. 1 resetn sd00224 figure 3. reset timing a1a6 r/wn csn d0d7 dtackn 2 3 5 4 6 8 9 11 7 12 13 14 sd00225 figure 4. bus timing (read cycle) x1/clk dtackn command valid sd00226 figure 5. command timing
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 10 a1a6 rwn csn d0d7 dtackn 2 3 5 4 6 12a 12 13 10 7 14 sd00228 figure 6. bus timing (write cycle) 15 irqn iackn d0d7 dtackn 8 11 7 7a sd00229 figure 7. interrupt cycle timing
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 11 csn gpo1n and/or gpo2n csn dtack old data new data rwn gpi1n and/or gpi2n rwn 18 17 16 sd00230 figure 8. port timing v m v ol +0.5v v ol csn irqn 19 sd00231 figure 9. interrupt timing x1/clk ctclk rxc txc +5v 470 w x1 x2 x2 14.7456 mhz x1 c1 c2 driving from external source duscc clock to other chips 1k +5v crystal series resistance3 should be less than 180 w c1 = c2: 0-5pf + (stray < 5pf) 20 20 sd00232 figure 10. clock timing
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 12 1 bit time (1 or 16 clocks) txd txc (input) txc (1x output) 21 22 sd00227 figure 11. transmit timing rxd 23 24 synout synin rxc (1x) input sd00233 figure 12. receive timing iackn idcn 25 sd00234 figure 13. interrupt daisy chain timing
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 13 txdakn d0d7 rdyn (dtackn) dtcn donen (input) txdrqn donen (output) 39 30 36 37 32 31 28 27 38 40a 40 sd000235 figure 14. dma transmit write timingesingle address dma mode rtxdakn d0d7 rdyn (dtackn) dtcn donen (output) rtxdrqn 34 26 29 30 28 27 32 31 40a 33 35 sd00236 figure 15. dma receive read timingesingle address dma mode
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 14 41 42 donen (output) csn dtackn donen (input) txdrqn transmit dual address dma mode 44 43 donen (output) (eom) rtxdrqn sd00237 figure 16. dual address dma mode timing
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 15 dip48: plastic dual in-line package; 48 leads (600 mil) sot240-1
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 16 plcc52: plastic leaded chip carrier; 52 leads; pedestal sot238-3
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 17 notes
philips semiconductors product specification SCN68562 dual universal serial communications controller (duscc) 1995 may 01 18 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 2000 all rights reserved. printed in u.s.a. date of release: 01-00 document order number: 9397 750 06825

data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

▲Up To Search▲

Price & Availability of SCN68562

	To Download SCN68562 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .